Class toastoven with a hierarchical state machine used in the following examples of code generation Statesmith is a cross platform, free/open source tool for generating state machines in multiple programming languages The generated code is human readable, has zero dependencies and is suitable for use with tiny bare metal microcontrollers, video games, apps, web, computers. When the model meets the design requirements, you then generate vhdl ®, verilog ® or systemverilog code that implements the design The state machine is defined using a basic json string, and includes convenience timers. Logicblocks provides a source generator that can generate uml state diagrams of your code
Generated uml diagrams are placed alongside the code for your logic block with the *.g.puml extension You can use plantuml (and/or the plantuml vscode extension) to visualize the generated diagram code. And when i noticed how messy my old gui code was and then found this pattern, i thought of giving it a shot In particular, my ideal interface for the hsm would look like this: State machine fundamentals this page has interactive examples to help you learn about statesmith state machines The examples use real code generated by statesmith from the svg diagrams below
